Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator
Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi, Toshiyuki Tsutsumi, Koji Yamazaki, Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2008
In this paper, faulty effects of interconnect opens in logic ICs fabricated with a 90㎚ CMOS process are analyzed by device simulation. In the analysis, it is examined whether a logical error can be caused at an opened input signal line by logic signals of the neighboring signal lines. The simulation results suggest us that a logical error may occur at an interconnect surrounding by 8 interconnects if the interconnects are longer than 5㎛ and the width of an open defect is greater than 2.0㎚.