Register architecture for multi-tasking systems
D. Richard Miller, Donna J. Quammen · 1996
The potential for high context switch overhead discourages architects from using large register files in RISC processors. This limits the number of registers in systems even though registers are high bandwidth storage over which the compiler can have complete control. Threaded Windows systems address this problem by providing a mechanism for dynamically allocating register resources to tasks based upon their needs. This allocation accommodates the dynamic behavior of a system regardless of its breadth (number of tasks) and depth (call depth) requirements. This is especially important for embedded systems where system design methods use tasks as a natural part of the functional decomposition process. The Threaded Windows approach is evaluated using a version of Stanford University's Architect's Workbench which has been modified to run pre-emptive multitasking benchmarks. In these simulations a threaded register set is shown to yield a significant reduction in memory reads and writes with a three to four fold mean reduction in off chip traffic when compared to single register sets and overlapping window register sets of comparable physical size.