Design of a Starlite Switching Network
Pilok Lim, K.R. Adams · 1987
The design of part of a wideband packet-switching network is reported. Based on AWA's NMOS technology, two designs are examined. The first design, a PLA circuit, was readily designed but occupies about twice the area and dissipates about 2.5 times the power of the second design. The second circuit, based on random logic, was much more time-consuming to design and is somewhat less tolerant to process variations than the PLA circuit. The design comparsions are for the case of 8-line switch modules operating at clock frequencies of 5 - 10 MHz and taking account of variations in threshold voltages in the ranges Vte = (0.8 - 1.3) V and -Vtd = (3.5 - 4.5) V.