A cell synthesis method for salicide process [CMOS logic]
Kazuma OKADA, Takayuki Yamanouchi, T. Kambe · 2002
Our method utilizes the local interconnect between adjacent transistors, which is available in some salicide processes, and optimizes the transistor placement of a cell considering both area and the number of local interconnects. In this way we reduce the number of metal wires and contacts, The circuit model is not restricted to conventional series-parallel CMOS logic, and our method enables us to synthesize CMOS pass-transistor circuits, Experimental results show that our method uses the local interconnect effectively, and optimizes both cell area and metal wirelength.