Timing error analysis of flooded LDPC decoders
Alexandru Amaricăi, Valentin Savin, Oana Boncalo, Nicoleta Cucu Laurenciu, Joyan Chen, Sorin Cotöfană · 2015
In this paper we perform a fault tolerance assessment of flooded Low Density Parity Code (LDPC) decoders affected by probabilistic timing errors, characteristic to sub-powered CMOS circuits. We investigate the error correction capability - in terms of Frame Error Rate (FER) - of faulty flooded Min-Sum (MS) and Self-Corrected Min-Sum (SCMS) LDPC architectures for both Binary Input Additive White Gaussian Noise (BIAWGN) and Binary Symmetric Channel (BSC) channel models and flooded FAID architectures for BSC channel model. The analysis is performed using a multi-level fault injection methodology, which accurately captures the probabilistic error profile of each combinational and memory blocks' output, according to the different clock constraints. The analysis indicates that the LDPC decoders are capable to correct errors affecting the internal data-path, not only those which appear in the transmission channel. Furthermore, the decoder potential to increase throughput by means of overclocking has been estimated to be between 77% and 150%, while preserving the nominal error correction performance.