An Area-Efficient Integrated Architecture of Transform Circuit for WMV9/MPEG-4/H.264 Video Decoder
Seonyoung Lee, Kyeongsoon Cho · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2007
This paper proposes the new circuit architecture to integrate the IDCT operations of three most popular video compression standards: WMV9, MPEG-4 and H.264. The core of the proposed architecture is the concept of the delta coefficient matrix which exploits the similarities of the IDCT coefficients of WMV9, MPEG-4 and H.264. We implemented the integrated IDCT circuit based on this architecture using only adders and shifters, verified its operation on the FPGA board and synthesized the gate-level circuit using 130㎚ standard cell library. The synthesized circuit has 45,814 logic gates and its maximum operating frequency is 123.1㎒.