Design of a Scalable Systolic Synchronous Memory
Gab-Joong Jeong, Kyoung Hwan Kwon, Moon-Key Lee · Journal of Electrical Engineering and Information Science · 1997
This paper describes a scalable systolic synchronous memory for digital signal processing and packet switching. The systolic synchronous memory consists of the 2-D array of small memory blocks which are fully pipelined and communicate in three directions with adjacent blocks. The maximum delay of a small memory block becomes the operation speed of the chip. The array configuration is scalable for the entire memory size requested by an application. It has the initial latency of N+3 cycles with N×N array configuration. We designed an experimental 200 ㎒ 4Kb static RAM chip with the 4×4 array configuration of 256b SRAM blocks. It was fabricated in 0.8㎛ twin-well single-poly double-metal CMOS technology.