A multi-digital signal processing architecture for fast Fourier transform implementation
K.M. Curtis, N. Ladjeroud · 1990
A hybrid parallel and sequential architecture may be the optimum solution to the calculation of the FFT. The authors have constructed such a system consisting of three TMS 320C25 digital signal processors. Two of the processors work in parallel, performing 256-point radix-4 decimation in frequency 'in place' complex FFTs. The third processor combines the outputs of the other two processors thus forming the full 512-point FFT. It also performs the unscrambling of the data from the preceding processors and the digit reverse procedure prior to outputting the results. The system has been constructed on two IBM PC/AT plug-in cards with the interfacing to the IBM being carried out via its I/O ports.