Low latency, High throughput and Less complex VLSI architecture for 2D-DFT
Sohil Shah, Preethi Venkatesan, Deepa Sundar, Muniandi Kannan · 2008
This paper proposes a pipelined, systolic architecture for two-dimensional discrete Fourier transform (DFT) computation which is highly concurrent. The architecture consists of two, one-dimensional DFT blocks connected via an intermediate buffer. The proposed architecture offers low latency as well as high throughput and can perform both one-and two-dimensional DFTs. The architecture supports transform length that is not power of two and not based on products of co-prime numbers. The simulation and synthesis were carried out using Cadence tools, NcSim and RTL Compiler respectively, with 180 nm libraries.