Design of Partially Reconfigurable Computing System and Implementation on Virtex-4 FPGA
Sandeep Sharma, Ashutosh Gupta, Manoj Duhan, Kota Solomon Raju · SSRN Electronic Journal · 2010
The paper presents the methodological algorithm of partial reconfiguration flow for execution and implementation of Reconfigurable Modules (RMs) on Xilinx Virtex-4(XC4VFX12) device. Its interface controller through UART for 32-bit RM was designed. An interactive interface was created for a system designed with static as well as dynamic parts. Using this interface, operands are assigned to the 32-Bit arithmetic and logical RMs at run-time. The dynamic part included the two reconfigurable regions which were allocated to execute various logical and 32-bit arithmetic modules in a time-shared manner. Static part was the region of the design that did not change during partial reconfiguration and contained the logic to control the partial reconfiguration process. To verify partial reconfiguration execution at runtime, an interface was designed to make user interaction with the system at run-time. Interface design included the controllers for controlling the flow of data to and from the reconfigurable modules to the external world (host environment) through bus macros. The controllers were designed as static modules. All the modules, static as well as dynamic were designed and simulated to verify the functionality with supporting simulation tool using ModelSim-6.0d and synthesized with Xilinx 9.1.02i_PR10 (ISE).