A dual-ported real memory architecture for the g-machine
L. Rankin · 1986
A Dual-Ported Real Memory Architecture for the G-machine Linda J. Rankin Oregon Graduate Center, 1986 Supervising Professor: Richard B. Kieburtz A dual-ported real memory architecture is described which supports the requirements of a list-processing evaluator, the G-machine. The architecture pro. vides support for allocating avails.ble nodes and a concurrent garbage collection scheme. This scheme uses reference counts and requires traversal of sub-graphs to collect cyclic structures. The architecture requires only one customized hardware component that provides support for maintaining reference counts. Simulation of the architecture shows that it is efficient and meets the requirements of the Gmachine given certain assumptions about the number and size of sub-graphs that are traversed. Cyclic structure information provided by the compiler would reduce the number of sub-graphs requiring traversal. Simulation shows that this optimization improves performance of the design, particularly for allocation rates greater than lOOK nodes per second.