The Joint FPGA Implementation of the Grostl Hash Algorithm and AES
J. Douglas Brodie, Howard M. Heys · 2011
In November 2007, NIST announced an open competition to select a new cryptographic hash algorithm, referred to as SHA-3, and, in December 2010, the five finalists were announced. One of these finalists is the hash algorithm, which has been designed to incorporate features of the Advanced Encryption Standard [1]. In this paper, we investigate the joint Grostl/AES implementation proposed by Jarvinen [2] targeted to a Xilinx FPGA device and present results on the number of FPGA resources required for the datapath design. [1] Gauravaram, P., et al., Grostl - A SHA-3 Candidate, submission to the NIST SHA-3 Competition 2011. [2] Jarvinen, K., Sharing Resources Between AES and the SHA-3 Second Round Candidates Fugue and Grostl, presented at the Second SHA-3 Candidate Conference, 2010. [Student Paper Award]