Low Cost PLD with High Speed Partial Reconfiguration
Naoki Hirakawa, Masanori Yoshihara, Masayuki Sato, Kazuya Tanigawa, Tetsuo Hironaka · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2008
Recently, Field Programmable Gate Arrays (FPGAs) have been used for implementing various types of logic functions. But the conventional FPGAs have the following problems. The conventional FPGAs include switch matrixes for programmable connection, but the switch matrix occupies a significantly large area of the FPGA. As another problem, the configuration speed is slow because of the serial configuration method. To resolve these problems, we proposed MPLD as a new Programmable Logic Device (PLD) architecture which introduce MLUT instead of the conventional LUT. In MPLD each MLUT can be used as a combination logic, memory and switch matrix, on the demand of the mapped circuit. The merits of MPLD are the following. 1) MPLD can behave as both the reconfigurable device and the conventional parallel memory. 2) Implementing cost of MPLD is cheaper than the conventional FPGAs, because MPLD does not need switch matrixes as the conventional FPGA does. 3) The configuration speed is fast and partial configuration is easy because configuration method of MPLD is same as write access of the conventional parallel memory. In this paper, we present the MPLD architecture and its evaluation results of the prototype MPLD chip.