MPSoC Design Space Exploration Based on Static Analysis of Process Network Model
Yongjin Ahn, Ki‐Young Choi · Journal of the Institute of Electronics Engineers of Korea · 2007
In this paper, we introduce a new design environment for efficient multi-processor system-on-chip design space exploration of signal processing applications. The design environment takes a process network model as input system specification. The process network model has been widely used for modeling signal processing applications because of its excellent modeling power for such applications. However, it has limitation in predictability, which could cause severe problem for real time systems, thus other models of computation such as synchronous dataflow are preferred in some cases, even though they have limited modeling power. This paper proposes a new approach that enables a static analysis of a process network model by converting it automatically to a synchronous dataflow model hierarchically combined with finite state machines. For efficient design space exploration in the early design step, mapping application to target architectures has been a crucial part for finding better solution. In this paper, we propose a mapping system which enables not only fast single objective optimization but also multiobjective optimization using an evolutionary algorithm. Our mapping system supports both single bus architecture and multiple bus architecture in which general-purpose processors, digital signal processors, shared memories, etc. are connected by a bus matrix. In the experiments, we show that the automatic conversion approach of the process network model for static analysis is performed successfully for several signal processing applications, and show the effectiveness of our mapping algorithm for both single objective optimization and multiobjective optimization by comparing it with previous approaches.