A New Clock Skew Scheduling Methodology for High-Level Power Optimization
Chi-Ho Lin · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2009
In this paper, we present a new clock skew scheduling methodology for high-level power optimization to optimize the power consumption in the synthesized data path. In this paper, The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, we plans for the clock skew scheduling in physical design stages during register binding. At the same time it ensures not invalidating the subsequent clock skew scheduling for optimizing the clock period. We use the switching power as the native objective of our register binding problem. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.