Development of Heterogenous Multi-core Processor ”Hy-DiSC” with Dynamic Reconfigurable Processor
Uchida Takuro, Nishinaga Yasuhiro, Tetsuya Zuyama, Kazuya Tanigawa, Tetsuo Hironaka · ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications · 2008
For accelerating multimedia applications by streaming, we have proposed the heterogeneous multicore processor Hy-DiSC with dynamic reconfigurable processor DS-HIE. The goal of the Hy-DiSC processor is to achieve high performance in a small chip area. In this paper, the performance improvement of the Hy-DiSC processor adopting the DS-HIE processor was evaluated. The application programs that selected for performance evaluation was a JPEG encoding process and the 2-D DCT included in the JPEG encoding process. And, the DS-HIE processor accelerates the 2-D DCT included in the JPEG encoding process. As a result, compared with the MeP processor the DS-HIE processor achieved 28 times higher performance on the execution of 2-D DCT. And, the DS-HIE processor requires fewer transistor counts to implement it.