Reduction of power consumption during test applicationby test vector ordering
Patrick Girard, C. Landrault, S. Pravossoudovitch, Daniel Séverac · Electronics Letters · 1997
The authors address the problem of testing VLSI circuits without exceeding their power ratings during testing. The proposed approach is based on re-ordering test vectors in a test sequence to minimise the switching activity of the circuit during test application. Results of experiments are presented which show a power reduction in the range 7.5–55.8% during test application.