Design verification and emulation of a multichip high-speed GaAs RISC processor using soft-programmable logic
Steven R. Carlough, S.A. Steidl, A. Airapetian, A. Garg, C. Maier, P. Campbell, Hans J. Greub, John F. McDonald · 2002
Soft-programmable logic is increasingly used to emulate and verify CMOS designs before fabrication. The F-RISC emulator uses this technology to emulate and verify a multichip GaAs RISC processor. An essential part of the F-RISC emulator is the mapping of the differential CML GaAs libraries to the Xilinx FPGA libraries. The emulator helped to detect several design errors.