Méthode de conception rapide d'architecture massivement parallèle sur puce : de la modélisation à l'expérimentation sur FPGA
Mouna Baklouti · HAL (Le Centre pour la Communication Scientifique Directe) · 2010
The main purpose of this PhD is to contribute to the design and implementation of high-performance Systems on Chip to accelerate and facilitate the design and execution of systematic data parallel applications. A massively parallel SIMD processing System-on-Chip named mppSoC is defined. This system is generic, para- metric in order to be adapted to the application requirements. We propose a rapid and modular design method based on IP assembling to construct an mppSoC configuration. To this end, an IP library, mppSoCLib, is imple- mented. The designer can select the necessary components and define the parameters to implement the SIMD configuration satisfying his needs. An automated generation chain was developed. It allows the automatic generation of the corresponding VHDL code of an mppSoC configuration modeled at high abstraction level model (in UML). The generated code is simulable and synthetizable on FPGA. The developed chain allows the definition at a high abstraction level of an mppSoC configuration adequate for a given application. Based on the simulation of the automatically generated code, we can modify the SIMD configuration in a semi-automatic exploration process. We validate mppSoC in a real video application based on FPGA. In this same context, a comparison between mppSoC and other embedded systems shows the sufficient performance and effectiveness of mppSoC.