Reliability of Memories Built From Unreliable Components Under Data-Dependent Gate Failures
Srdan S. Brkic, Predrag Ivaniš, Bane V. Vasic · IEEE Communications Letters · 2015
In this letter, we investigate fault-tolerance of memories built from unreliable cells. In order to increase the memory reliability, information is encoded by a low-density parity-check (LDPC) code, and then stored. The memory content is updated periodically by the bit-flipping decoder, built also from unreliable logic gates, whose failures are transient and data-dependent. Based on the expander property of Tanner graph of LDPC codes, we prove that the proposed memory architecture can tolerate a fixed fraction of component failures and consequently preserve all the stored information, if code length tends to infinity.