An Efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli
Ming‐Hwa Sheu, Su-Hon Lin, Chichyang Chen, Shyue-Wen Yang · 2004
In this paper, we present a new four-moduli set and an efficient residue to binary (R/B) converter design. The merits of the proposed four-moduli set in- clude 1) larger dynamic range; 2) higher degree of parallelism for conversion; 3) balanced bit-width for internal RNS arithmetic op- erations; and 4) flexible moduli set selection. According to the re- lation between the proposed moduli, the divide-and-conquer tech- nique is used to design a two-level converter architecture which has lower hardware cost and shorter critical delay. For the R/B converter designed with 12-b , our architecture has about 47% saving in hardware cost and 40% saving in critical delay com- pared to the last work (8).