AnArea-Efficient VLSI Architecture forReed-
Yanfei Guo, Zhan-Cai Li · 2005
Inthispaper, theknowndecoding procedure forReed-Solomon (RS)codeisanalyzed inthewayofvector operations thataresuitable forVLSIimplementation and pipelining. Then,a newarea-efficient architecture forRS decoder isproposed. Thenewarchitecture canimprove the reuserateofmaincomputation unit, reducethehardware complexity anddelete theredundancy circuit. Theresults showthatthetotal numberofgatesoftheproposed RS (204,188) decoder isabout27,000 gates, whichisabout39% smaller thanthesamekindofconventional ones.Ithasbeen integrated inachannel demodulation chipforhigh-definition television (HDTV)andthechiphasbeentested successfully in practice.