Circuits and Systems Letters Finite Gain-Bandwidth Product Effects on a Pair of Pseudo-N-Path SC Filters
J. L. · 1984
A detailed analysis of two novel SC pseudo-N-path filters 131, (4) are presented to determine the effects of their transfer functions due to .the op amp gain-bandwidth product (GB). To appreciate the difference between the two filters, z-plane root locus plots as a function of GB/f,. are presented. An approach to implement narrow-band comb filters is by means of the N-path concept (l). Switched-capacitor techniques can be easily incorporated with the N-path filters to realize practical monolithic filters. The basic N-path concept involves N ideally identical SC low-pass filters (2) that are cyclically oper- ated each at the low frequency fc and the input signal is sampled at a higher clock frequency Nfc. Unfortunately, with true N-path filters a number of unwanted image frequencies is generated, since in practice the N individual paths are not matched per- fectly. Besides this problem, there is clock feedthrough at the signal frequencies. The pseudo-N-path filters have been proposed to eliminate these problems (3), (4). In this approach each feed- back capacitor is replaced by a circulating shift register. The RAM-type shift register reported in (3) eliminated the matching problem. An alternative realization for a shift register that pro- vides a solution to both mismatching and clock feedthrough problems is proposed in (3). Fig. 1 shows a three-path time multiplexed SC N-path filter with inversion. This circuit (3) is a modification by Patangia and Cartinhour (5). Another novel circulating shift register (4) with favorable discharge time, en- abling the filter to theoretically operate at a relatively high frequency is shown in Fig. 2. In this paper we compare these two novel SC pseudo-N-patch filters. It is shown that when the op amps are modeled with one dominant pole, their frequency responses differ significantly. To illustrate the difference between the shift registers, a numerical example is considered. The design factors are: a center frequency f0 =l kHz, a sampling frequency fc = 6 kHz, and N = 3. The circuit of Fig. 1 uses one op amp and 4 clock phases. CZp was included to simulate the parasitic capacitance of the topology at that node. Fig. 2 involves 3 op amps and 2 clock phases. The circuits were analyzed assuming all the op amps have the same GB and are characterized by a dominant pole. The analysis of Fig. 1 involves one circuit analysis for each phase. The equation characterizing any of the four circuits is a linear differential equation, the initial conditions are naturally different at each phase. The step response of any simple op amp SC circuit is an exponential ramp. For an ideal op amp, i.e., GB + 00 the step response would be another step. The complete description of the analysis requires the solution of four simultaneous differential equations. In the case of Fig. 2, the analysis involves the solution of three differential equations (one for each op amp) for each of