Tutorial (T-1) Functional Verification 2003: Technology, Tools andMethodology
Carl Pixley, Aruna Chittor, Fred Meyer, Steve McMaster, Dan Benua · 2003
Functional verification is a key bottleneck in the costeffective design of integrated circuits. It is estimated that ver@cation in its entirep accormts.for up to 60% ofdesign resources, including duration. coinputer resources and total personnel. The three priiiiaiy methods used in logic and fiincrional veriQcation of commercial integrated circuits are siniulation, emulation and foimal ver@ztion. While it is notpossible to coinprehensively survey thefield in a short space, currentpractice in isolated aspects ofall tkiee hyes ofveriJication are discussed. All design arid i!er(fication tools work on a model of a clesigii, .for esuriiple. transaction, register tracsfer (Rr), gate, switck and transistor models. These models are defined b,y the seiiiuntics of rhe languages that describe the niodels. Buf it is not the purpose of this paper to discuss language, hut inore to discuss technologies. methodologies arid applications. h the last .five years the verification Iaiirlscape has changed somewhat. We will emphasize these changes. For esaiiiple, rhe rise oftestbench languages, the use of assertions and constraints -- rather than golden models -- and various iiiipro~~eriierits to formal verification