Embedded Memory Design for a Four Issue Superscaler RISC Microprocessor (Invited)
Toshinari Takayanagi, K. Sawada, Takayasu Sakurai, Yukiko Parameswar, Shigeru Tanaka, Nobuyuki Ikumi, Masato Nagamatsu, Yoshihisa Kondo, K. Minagawa, J. Patrick Brennan, Peter Hsu, Paul K. Rodman, Joe Bratt, Joe Scanlon, Mankit Tang, Chandra Joshi, Monica Nofal, Komukai Toshiba-cho · 1994
Design of embedded memories for a 64 bit superscaler RISC microprocessor is described. Since the microprocessor issues four instructions per cycle including two memory operations at a time, very wide bandwidth of the primary caches: 2.4 GB/sec is vital. The chip includes 16 KB instruction cache, 2 KB branch cache, 16 KB dual ported data cache and 384 entry dual ported TLB. Unique scheme of TLB hit check greatly reduces critical path. The chip is fabricated in Toshiba's high-speed 0.8 pm CMOS technology utilizing triple metal and triple well. The die size is 17.3 mm x 17.3 mm and contains 2.6 million transistors. The chip achieves 75 MHz at 70 'C