OVER 100dBcROM-LESS PIECEWISENON-LINEAR DIRECT DIGITALFREQUENCY SYNTHESIZERS
Valeriu C. Beiu, MinSheng ERoad · 2004
This paperdeals withmaximizing thespurious treedynamic range(SFDR), while alsominimizing the powerconsumption ofsine-wave approximation circuits usedindirect digitalfrequency synthesizers. Three new16- segment ROM-less piecewise non-linear approximations are introduced andcompared withmanyother ROM-less voltutions, Thecircuit complexity (estimated asthenumber of transistorso iscomparable tothatofother16-segment piecewise linear approximations, whiletheSFDR is significantly increasedfrom 4872dBctoover100dBc. I.INTRODUCTION A Direct Digital Frequency Synthesizer (DDFS) generates high-resolution, fast-switching frequencies, andiswidely usedinmodemcommunication systems. Theessential components ofaDDFSare: thephase accumulator, aphase- to-sine approximation circuit (referred toasapproximation circuit), adigital-to-analog converter, andalowpass filter. Themajordesign constraints ofa DDFSarepower con1suml)tion anduriousfiree dynamic range (SlDlR). *Thepower consumption should beminimized. *Thespurious free dynamic range(SFDR) should be maximized Thiswas considered equivalent to minimizing themaximum absolute error (MAE), butitis notentirely true. Boththese constraints arestrongly affected by: * theprecision used (innlumber ofbits); atid * thea;)proximaltion mtiethlodt/circuit used. Thispaper will start byshortly presenting thlese recent ROM-less solutions. Allofthemarebased onpiecewise linear approximations ofthesine. Wewill then introduce an alternative solution topiecewise linear approximiiation, namely the useofpiecewise non-linear approximations. This provides greater accuracy (than linear approximations) for thesamenumber ofsegments, while theapproximation circuit isnottoocomplicated. Three different piecewise non- linear approximations willbe introduced, andtheir simulation results will bepresented. A detailed comparison ofseventeen DDFSsusingdifferent approximation methods/circuits (including thethree newly introduced ones) willbepresented ina compact tabular forn. Finally, hardware design constraints will beidentified, andsolutions forovercoming themwillbeproposed. Conclusions and future direction ofresearch areending thepaper.