APPLICATIONS DRAM FRAME MEMORY FOR STAND-ALONE
Klaus Hemnann, J. Hilgenstock, P. Pirsch · 1998
A video coding subsystem for monolithic integration in a 0.25 pm CMOS technology has been developed. It consists of a programmable video signal processor core, up to 8 Mbit frame memory as embedded DRAM and video interfaces. The functionality of all major components has been verified by implementation on test chips in 0.5 ym CMOS technology. A system realization in 0.25 pm CMOS technology is planned. Investigations show that a die size of less than 89 mm2 for a single chip implementation can be achieved.