Fault Simulation of Parametric Bridging Faults in
Cmos Ic, Marcello Dalpasso, Michele Favalli, Piero Olivo, B. Riccb · 1993
The fault simulation of resistive faults in- side complex CMOS macro-gates requires proper evaluation of resistances, in order to correctly determine realistic fault cov- erages. To this purpose, the present work illustrates a novel approach applicable to a large category of faults (bridgings, transistor stuck-ons and node stuck-ats) giving rise to resistive paths between power-supply and ground, hence being all indi- cated by the general term of bridging Such a method, avoiding single-fault injection procedure, consists of a fault analysis performed inside macro-gates aimed at determining the threshold resistance discriminating whether or not a given fault is detectable as a logic error; this analysis is performed inside CMOS macro-gates whose output is observable, as determined by means of any method andlor simulator. Finally, to fully characterize the quality of a test sequence with regard to resis- tive faults, a new definition of fault coverage is pre- sented, because the common concept of fault detection is not applicable to parametric faults.