Algorithms rorDetection ofFaults inLogic Circuits
Combinational Diagnosis · 1971
Programmed algorithms fortestgeneration andtestevalua- tionaredescribed. TheD-notation isintroduced anda testgenerator (DALG)forcombinational logic ispresented. Thesequential caseisthen examined. Reallife constraints related toLSItesting arediscussed. Two heuristic testgenerators satisfying theseconstraints areintroduced. The iterative testgenerator (ITG) generates testsbytransforming thegiven sequential circuit intoan iterative combinational circuit. Themacroblock testgenerator (MTG)usesthesameapproach butmakesuseofcomplex primitives (latches, triggers, etc.) torepresent thecircuit tobetested. Both theITGandtheMTG arenotalwaysguaranteed togenerate goodtests foreachexamined failure, andareusedinconnection witha testevalua- tor(simulator). Basicfeatures ofthisevaluator arediscussed. IndexTerms-DALG, fault location, logic circuit diagnosis, logic test- ing,test generation.