Performance Analysis of Routing Algorithms
Lokesh M. Heda, N P. Narkhede · 2012
As an emerging and advanced technology, Network-on-Chip (NoC) may become the alternative of the traditional bus-based System-on-Chip (SoC). In an interconnection network structure, interconnected routers are the core of the whole system and the network's performance mainly depends on their performance. There are many significant factors which determine the working mechanism of a router and its performance, such as topology, switching strategy, routing algorithm, and flow control mechanism. The switching mechanism plays a vital role to move the data from an input channel and place it on an output channel. Virtual cut through (VCT) and wormhole (WH) switching techniques are widely used in NoC architecture. In this paper, Wormhole and VCT technique has been proposed for Network on chip architecture and its performance is analyzed using the parameters such as area and speed. In this paper the designing and implementation of Wormhole and Virtual Cut through router have been discussed. The simulation of Wormhole system and VCT is done in Modelsim-SE as a simulation & debugging tool. The design is synthesized in Xilinx ISE 9.1i as well as in Quertus 8.1 for the packet size of 16 bits (0-15) on the platform of family automotive spartan2 for device-XC2S200, PQG208 package and speed -5.