Embedded Test and Debug of Full Custom and Synthesizable Microprocessor Cores
Andrew Burdass, G. Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York · 2000
This paper compares and contrasts two very different approaches to testing cached CPU macro-cells that are typically embedded in a System on Chip (SoC). One uses a test bus to apply functional vectors, while the other uses a combination of scan insertion, memory BIST and test collars. IP protection issues and non-intrusive tracing are also discussed.