Signal and Data Processing Circuits
Earl E. Swartziander · 1984
Processors for signal and data processing need more and better VLSl! Such processors can benefit directly from the development of improved arithmetic and memory circuits. Improvementsare essential for speed and functionality. The development of new ICs for general systems applications center on three critical areas: whether the circuit implements a widely used function, if an efficient VLSl design is possible for the circuit, and if the resulting performance will be better than with existing approaches. The circuits to be discussed accent positive achievements on the foregoing requirements. In a pair of discussions centered on arithmetic, speakers will describe a 45ns multiplier and a 25/50MHz multiplier/accumulator. Both realize multiplication, which represents 30-50% of the arithmetic of digital signal-processing systems and 16% of the arithmetic of the Gibson mix; a standard data processing instruction mix. As shown multiplication algorithms are highly regular: thus they are amendable to cellular design, where only a few types of cells are designed to create a complete function. The cells are replicated in one or two dimensional arrays to realize the multiplication function. In optimizing the design of the 16x16 multiplier, Kaji, et. al., Booth's algorithm is used to generate partial products and a Wallace tree to sum the products. The result is somewhat less regular than the standard successive addition algoriahm, but much faster. In contrast, Welten, et. at., have used pipelining to improve the performance of a multiplier/accumulator. A transparent register separates the multiplier from the accumulator. When the register is used the chip throughput doubles, but the register can be disabled when ease of use is most important. Clearly both of these circuits offer a substantial increase in performance relative to the current state-of-the-art, 16x16 multiplication in lOOns at 3W. Further reports will cover the development of a floating-point multiplier and an SOS-based 27ns multiplier.