F.P.G.A Implementation of Way Tagged Cache into Chip Multiprocessors
Minu Senan, Babu P Kuriakose · 2014
Abstract— Energy consumption has become a critical issue in many high performance microprocessors. Chip multiprocessors, CMP is only way to build high performance microprocessors. Most of the power dissipated in microprocessor is contributed by on chip cache memories. This paper includes a CMP architecture in which way tagging is applied to cache memories for reducing energy consumption. A two core processor architecture with a shared L3 cache has been selected. For each core, the way information of L2 cache is maintained in the L1 cache and that of L3 cache in L2 cache. The IO power report after implementation shows that about 50% of power reduction can be achieved by including way tagging into CMP architecture compared to conventional CMP.