Front Side Bus
Tung Pham, Brian Koehler, Daniel Young, Louis Bushard · 2006
TM Processor is a complex design with many multi-gigahertz, synchronous and asynchronous clock domains. One of the key design features is the high speed Front Side Bus I/O system that consists of analog and digital elements that provide an interesting manufacturing test challenge for a low test cost, high volume, and high quality ship level application. This publication will focus on the test solution for the high speed custom logic that aligns the source synchronous clock to the associated receiver data.