An FPGA based Accelerator for Encrypted File Systems
Adrian Matoga, Ricardo Chaves, Pedro Tomás, Nuno Roma · 2011
In this work, the possibility of application of an AES coprocessor to increase the performance of encrypted file systems is examined. A brief description of an architecture based on an FPGA connected to a GPPU using PCI Express is followed by the preliminary evaluation of its performance compared to a software-only solution, as well as a discussion of bottlenecks and ways to deal with them.