Estimation of Maximum Power Spurious for Sequential Circuits Considering Transitions
Chuanyu Wang, Kaushik Roy · 1997
With the high demand fOT reliability and performance, accurate estimation of maximum instantaneous power dissipation in CMOS circuits is essential to determine the IR drop on supply lines and to optimize the power and ground routing. Unfortunately, the problem of determining the input patterns to induce maxlmum current, and hence, the ' um power, zs NPcomplete. Even for circuits with small n of primary inputs (PI's), it 8s CPU time intensive to conduct exhaustive search in the input vector space. In this paper we present an Automatic Test Generation (ATG) based technique to eficiently generate tight lower bounds of the maximum instantaneous power for CMOS sequential circuits under non-zero gate delays. Power dissipation due to spurious transitions has been considered by incorporating static timing analysis into the estimation process. Experiments were performed on ISCAS and MCNC benchmarks. Results show that the ATG-based technique is superior to the traditional simulation-based technique in both speed and performance. On an average, for sequential circuits having over 10,000 gates (ISCAS-89 benchmarks), the ATG-based approach executes 261 times faster, and generates a lower bound which is 1.8 times better compared to simulation based approaches.