ON TEST GENERATION FOR IDDO TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS
W. Scott Wayne, Bollinger Scott, F. Midkiff · 1991
This paper describes a test generation methodology that supports explicit IDDe test generation for unrestricted bridging faults in CMOS circuits. A modular, hierarchical approach is used to accurately represent the structure of CMOS design styles and manage complexity. Performance results are presented for a preliminary implementation of the approach.