On Testable Multipliers for Fixed-Width
Nilanjan Mukherjee, Jerzy Tyszer · 1995
The usage of multipliers in the increas- ingly demanding fixed-width data path architectures poses serious testability problems. Their truncated outputs not only degrade the fault observability, but the output re- sponses of multipliers are inadequate to completely test functional blocks that are driven by them. In this paper, we propose a new design for testability scheme to im- prove the overall testability of data paths. The methodol- ogy takes into account the truncated least signijcant bits of the product in the test mode to increase the variety of patterns at the output of a multiplier. The proposed techniques are part of the Arithmetic Built-in Self Test methodology and can be incorporated with a minimal per- formance degradation and area overhead. I. INTRODUCTION HE increasing applicability and complexity of data T path architectures necessitate the incorporation of sophisticated testability features in the design. Data path architectures are tested either by deterministic pat- terns or by means of built-in self test (BIST) schemes. Classical BIST techniques make use of circuit indepen- dent test pattern generators and test response com- pactors, thereby employing a test strategy completely orthogonal to the functional mode of operation. Conse- quently, it results in substantial area overhead and per- formance degradation. Recently, a new perspective has been created by a concept of Arithmetic BIST (ABIST), which exploits the inherent functionality of blocks in the data path to test the circuit itself (l), (2). The testing phase closely resembles the circuit functionality and re- quires virtually no area overhead or performance penalty for its implementation. Data path architectures generally comprise a network of powerful arithmetic and logic blocks such as adders, subtracters, ALUs, multipliers, comparators, etc. Be- havioral synthesis of testable data paths depends on the susceptibility of these functional blocks to pseudo- random patterns and their transparency in propagating the random patterns to the subsequent modules. Earlier observations reveal (2), (3), that multipliers which are This work was supported by a Cooperative Research and Devel- opment grant from the Natural Sciences and Engineering Research Council of Canada and Northern Telecom Ltd. very common in data paths, are not only difficult to test because of their truncated outputs, but also their fairly poor variety of responses makes it extremely difficult to test functional blocks that are driven by them. Previ- ous analysis of testable multipliers mainly concentrated on stand-slow blocks assuming that the entire output is observable (4)-(8). However, the increasing use of fixed width multipliers in large data paths makes it imperative to investigate techniques that improve the testability of both the multipliers and the entire system. In this paper, we propose a design for testability (DFT) scheme for multipliers that enhances the over- all testability of data path architectures. The proposed technique, which is a part of the ABIST methodology, improves the testability of fixed width multipliers, and increases the variety of patterns at their outputs as well. As a result, the functional blocks ihat are driven by the multiplier become easily testable. The modifi- cations proposed are based on residue number system arithmetic and introduces little area overhead and per- formance degradation into the data path.