TAM 7.2: A 100MHz 64-Tap FIR Digital Filter in a O.8jlm BiCMOS Gate Array
T. Yoshino, Paul Yang, Rajeev Jain · 1990
summary of devic e charaetcrist ics is shown in Table 1. The chip micrograph is shown in Figure 1. Aboul lwo thirds (49mm2) of the lOOk-gate array core was allocated to the filter. The design is equivalent to about S5k gates (2-input NAND gates) in complexity and utilizes 76')'0 of the core allo cation. Tbe device input/output are lOOK ECL compati ble. Figure 2 shows the functional switching waveforms of the master clock, LSR input, and MSB output al lOOMllz opera ling fre quency. Figure 3 shows the filter architecture implemented on the chip. The multiply-add operation in each tap is implemented by a ded icated shift-add scheme. The shift operation is accom plished by physically rouling (shifting) the dala inpul line Canonic signed digit (CSD) arithmetic is used to minimize the number of adders 2 . For example, a coefficient 0.875 (binary equivalent 2-1 + 2-2 + 2-3 is recorded as (l _2-3) in CSD repre sentation. A tap operation, Dk en) = Dk_l en) + 0.875X en), is reduced to Dk en) = DId en) f r X en) -2-3 X (n) 1 so