A Simultaneous Coefficient Calculation Method for FIR Filters
Mikio Shiraishi · 2003
A novel simultaneous coefficient calculation method for filter and its application to the filter design are de- scribed. This method can be applied to any ( ) stages of filters with no degradation of coefficient accuracy. Every coeffi- cient can be calculated by th-order multiple-loop accumulation of -scaled delayed impulses. The coefficient can be obtained every clock or operation cycle because these loops are not nested but merely chained together. decimation filters based on this method are suitable for high-speed operation as well-known cascaded integrator-comb (CIC ) filters. If rounding or truncation is used at data-accumulation stages, they can operate faster than those in some cases. For example, the critical-path-length ratio of 32-tap single-bit-input (for delta-sigma analog-to-digital converters) decimation filters by this and the CIC approach is 0.714 if their outputs are rounded to 8-bit words. Unfortunately, the gate count exponentially increases in proportion to the order . However, in some special cases (single-bit-input and decimation filters), they are comparable to the equivalent CIC filters in size.