On the Desi n of 0 timal FFult - Tolerant Systo FIP IC Arr y Architectures t
Asim J. Al-Khalili, Salim Hariri · 1991
In this paper we present a novel approach for designing highly reliable and optimal fault - tolerant systolic array architectures. In our approach, fault - tolerant algorithms are &signed by introducing redundant computations at the algorithmic level, so that when these algorithms are mapped into specific VLSI systolic array architectures, the architectures will be inherently fault tolerant. We introduce redundant computations in the original algorithm by creating diferent versions of the algorithm. The respective &pendency matrix (0) of the Merent versions of the algorithm are obtained and these are merged to give one &pendency matrix that rgects a given fault - tolerant requirement. This resultant depen&ncy matrix is nurpped into an optimal fault - tolerant systolic array using our proposed Space Time (S-T) systematic approach for mapping algorithms into optimal systolic architectures.