Design and Implementation of High efficient Two-variable KCM Multiplier
M G Ravikumar · 2014
In this paper, a high efficient Two-variable Constant Co-efficient Multiplier (KCM) is proposed. The multiplier is designed using Squarers which are designed using Vedic mathematics. This paper focuses on design, implementation and optimization of two- variable Constant Co-efficient Multiplier at algorithmic level. The proposed multiplier design is faster and much efficient than the existing system. The proposed architecture is implemented based on the two-variable Constant Co-efficient Multiplier algorithm to provide low power, area and high speed by design constraint trade-offs. The proposed design is designed and synthesized under ASIC domain using Cadence and functionally verified using Cadence RC Encounter RTL compiler tool. The proposed architecture consumes 23% less power than the existing architecture.