Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed
Andrew S. Waterman · 2011
Delivering the instruction stream can be the largest source of energy consumption in a processor, yet loosely-encoded RISC instruction sets are wasteful of instruction bandwidth. Aiming to improve the performance and energy efficiency of the RISC-V ISA, this thesis proposes RISC-V Compressed (RVC), a variable-length instruction set extension. RVC is a superset of the RISC-V ISA, encoding the most frequent instructions in half the size of a RISC-V instruction; the remaining functionality is still accessible with full-length instructions. RVC programs are 25 % smaller than RISC-V programs, fetch 25 % fewer instruction bits than RISC-V programs, and incur fewer instruction cache misses. Its code size is competitive with other compressed RISCs. RVC is expected to improve the performance and energy per operation of RISC-V. 1 1