A Virtual Simulation Environment For A Design And Verification Of A Gpgpu
Kwang Y. Lee, Tae-Ryoung Park, Jae-Chang Kwak, Koo, Yong S. · Zenodo (CERN European Organization for Nuclear Research) · 2011
When a small H/W IP is designed, we can develop an appropriate verification environment by observing the simulated signal waves, or using the serial test vectors for the fixed output. In the case of design and verification of a massive parallel processor with multiple IPs, it-s difficult to make a verification system with existing common verification environment, and to verify each partial IP. A TestDrive verification environment can build easy and reliable verification system that can produce highly intuitive results by applying Modelsim and SystemVerilog-s DPI. It shows many advantages, for example a high-level design of a GPGPU processor design can be migrate to FPGA board immediately.