A Simulation-based approach to Test Pattern Generation for
Paolo Enrico Camurati, Corno P. Prinetto, Matteo Sonza Reorda · 1992
Particular design environments, e.g., those based on Partial Scan, may prevent Design for Testability techniques from reducing testing to a combinational problem: ATPG for sequential devices thus remains a challenge. Random and deterministic structure-oriented techniques are state-of-the-art, but there is a growing interest in methods that resort to the automaton of the circuit. This paper presents SETA, a sequential test generator based on automata, an ATPG applicable to synchronous circuits working in fundamental mode. SETA generates test patterns while trying to disprove the equivalence of two automata. SETA is simulation-based: within the theoretical framework of the product machine, state-of-the-art simulation techniques are used to yield satisfactory experimental results on the ISCAS’89 benchmark set [l].