Location Circuit modification
E Combinational · 1996
logic hence showing that the proposed algorithms for ordering (and possibly inserting) flip-flops in the chain to reduce the register adjacency phenomenon8 are not a general solution. Based on our analysis, it appears essential to carefully choose the initial flip-flop states. We therefore propose a new algorithm, based on symbolic traversal techniques,'O and show that it fulfills this goal for FSMs corresponding to typica.1 control components. We can easily automate this approach and are currently integrating it into the industrial environment for ASIC design of Italtel, a major Italian tele- com systems manufacturer. This represents a real example of a design flow implementing a testable synthesis strategy. This article discusses in detail the CSTP architecture, sym- bolic algorithm, and the relative advantages and disadvan- tages of different approaches. Applying circular self-test path We considered whole circuits or embedded portions con- sisting of sequential blocks. In both cases, the following sim- plifying assumptions must hold on the portion of the circuit to which we apply CSTP: