Energy Efficient Partitioning Of Last Level Cache Memory with Cooling Management for Memory and CPU Subsystems
Vikas Kumar Sharma, J.M. Kumar · 2013
This paper presents a technique to improve the over- all performance of the multiprocessor chip. Efficient partitioning of last- level cache memory in a multi-processor chip can increase the performance significantly. The concept is to first allocate the fixed number of ways for a core and then forced the cache data to be way aligned so that a particular way is owned by a core at a particular time. At the time of access, cores cooperate with each other to migrate the ways between them so that a core has to consult only those ways which it has owns to find its data from which dynamic energy can be saved and unused ways can be power-gated for saving the static energy. This paper also presents a cooling management strategy for memory and CPU subsystems. It manages the temperature of memory and CPU subsystems by activating the memory and CPU actuators which does the required action in the subsystems of memory and CPU. It considers the thermal and power states of CPU and memory, thermal coupling between them and fan speed to arrive at energy efficient decisions.