Evaluation ofaPacket Switching Algorithm forNetwork on ChipTopologies using aXilinx Virtex-JI FPGAbased Rapid Prototyping System
Jürgen Becker, C. Bieser, Jürgen Becker, Klaus Dieter Mueller-Glaser · 2006
Duetotherising complexity ofmodernchipdesigns, theconnection ofthedifferent on-chip IPcoreshasbecomean important issue. Toestablish communication links between com- putation nodeseither widebusses orfastserial datapaths - so called networks onchip(NoC)-arenecessary, depending onthe application andthechipdesign. Incaseoftheserial links avari- etyofdifferent algorithms andtopologies arecogitable, which havetobeevaluated andtested tofind theoptimal solution fora given problem. Todothis, theNoCcanbeemulated onahard- wareplatform basedonFPGAstoexploit theflexibility forshort turn-around-times andachieve nearly realtimeconditions by accelerating thetest process. Ourapproach presents thecombina- tionofa flexible andversatile FPGA-based rapidprototyping system andefficient network onchip(NoC)implementation based onXilinx Virtex-It FPGAs.