A CONCURRENT BIST ARCHITECTURE FOR ONLINE INPUT VECTOR MONITORING
S. Devi Abirami, S. Paulin, S. Prabu Venkteshwaran · 2015
A Built-in self test techniques constitute a class of schemes that provide the capability of performing at speed testing with high fault coverage, whereas simultaneously they relax the reliance on expensive external testing equipment. Hence, they constitute an attractive solution to the problem of testing VLSI devices. BIST techniques are typically classified into offline and online. Input vector monitoring concurrent built-in- self test schemes perform testing during the normal operation of the circuit without imposing a need to set the circuit offline to perform the test. In this brief, a concurrent BIST Architecture scheme, which is based on the idea of monitoring a set of vectors reaching the circuit inputs during normal operation, and the use of a static-RAM like structure to store the relative locations of the vectors that reach the circuit inputs in the examined window; the proposed scheme shows the low power consumption than previously proposed schemes with respect to the hardware overhead and CTL (time required to complete the test) tradeoff.