Architecture aiid Perforiiiaiice of aii Electro-optical High Speed Packet Switch
G. Albert · 1990
A high speed packet switch based on VLSI chips and optical components is presented. The chips, located at tlie inputs of the switch, implement the routing algorithm, store tlie incoming packets, and control the access to the optical interconnection network, which connects inputs and outputs.. The simulation showed that up to two packets at a time must be traiisiiiitted on the optical interconnection network from any input to achieve optimal performance. The impact of this result on tlie chip complexity and on the transmission scheme used in the optical part is discussed, and a possible solution is outlined.